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Purpose-built for Silicon Debug and Failure Analysis
The V550 is Teseda’s flagship engineering test system designed specifically for design validation, silicon debug and failure analysis. With 512 I/O pins, 64Mb of pattern memory and 100 Mhz test rates in a desktop, air-cooled, 13.5 lb package, the V550 is the highest-performing benchtop engineering test platform in the industry. The V550’s comprehensive hardware features enable design and DFT engineers to debug and validate their newest and most complex SoC designs on their bench. Failure Analysis engineers can use the portable V550 to quickly diagnose quality and yield issues either testing devices stand-alone or coupled with advanced dynamic failure diagnosis equipment such as emissions microscopes, OBIRCH or LADA systems.
The Teseda V550 Engineering Test System
- 512 I/O pins with up to 100 Mhz frequency
- Supports functional and scan-based testing, BIST and IDDQ measurements
- 64Mb per pin pattern depth with up to 40Mb of acquire memory
- Flexible, per-pin timing capabilities for complex testing needs
- Works with our award-winning Teseda Workbench™ (TWB) DFT-enabled software
- DC parametric and Curve Tracing options
- Comprehensive fixturing and interfacing options
- Portable, lightweight and air-cooled - weighs just 13.5 lbs
V550 Features and Benefits
| 100 Mhz Performance | Validate your designs at full speed |
|---|---|
| 512 I/O Pins | Supports high pin count SoC devices |
| 64MB Memory | Run large ATPG patterns like stuck-at and transition fault scan tests without reloading |
| Works with all common ATPG tools |
Up and testing within hours, not days |
| Small, Air Cooled and Portable |
Easily fits in your Engineering or FA lab and always available to your team - 24/7 |
| Low Vibration Design | Highest quality dynamic imaging from emission microscopes and other FA diagnosis tools |
| Network Accessible | Share and access the tester remotely across multiple sites |
| Powerful Debug Software Tools | Reduce silicon debug time to days instead of weeks. Cut root failure analysis cycle time by as much as 80% |
V550 Applications
Desktop Silicon Debug and Failure Analysis
Perform full speed functional, stuck-at and transition fault testing. The V550 supports full per pin timing capabilities with up to 50ps of resolution and clock rates exceeding 200Mhz. Using the V550’s 64Mb pattern memory depth, execute large functional or ATPG –based scan patterns to quickly identify and diagnose device failures. Cut time to root-cause failure analysis by up to 80%.
DC Device Characterization
With the V550’s optional Parametric Measurement Option™ (PMO), characterize the DC performance of your device. Using the Teseda Workbench’s built-in interactive DC templates you can validate your device meets common DC specifications such as IiL, IiH, VoL and VoH.
With the additional DC Field Triage Package software option, add fully automated curve tracing capabilities as well as DC continuity and input leakage testing. Rapidly find common package faults such as broken or shorted bonding wires. Compare results against “golden” device data.
Emission Microscopy and Soft Defect Localization
The V550’s small size and low vibration make it a perfect fit for advanced dynamic failure analysis applications. The system is purpose-designed to fit inside of any emission microscope or overhead dock to common dynamic circuit analysis tools like the EmmiScope-III™. Easily loop around any set of failing vectors. Generate triggers at specific fail locations to synchronize your signal acquisition. The V550 is a perfect fit for your FA lab applications.
Dramatically Improve Debug Productivity and Failure Analysis Turnaround Time
The Teseda V550 engineering test system can increase your team’s productivity by empowering them with their own in-house design validation system, eliminating the extra time and expense of debugging on complicated production testers. Using the V550, your team can be up and testing first silicon in hours - not days. Get through silicon debug faster; validate test patterns sooner; without ever leaving the office.
Your FA teams can quickly confirm device failures seen in the field in their lab without waiting for results from the production floor. They can then isolate the logical design location of the failures, and quickly map to the physical X/Y location on the die using both software-based diagnosis and dynamic device probing techniques. Having a V550 in your failure analysis lab can dramatically reduce your overall turnaround time to root cause.