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Automated Diagnosis of Failing Chain Flip-Flops
Teseda’s Broken Chain Analyzer fully exploits the power of your existing DFT-based tests to automatically analyze captured tester fail logs and detect all common causes of scan chain failures - both hard (stuck-at fails) and soft (timing or voltage-related fails) down to the failing bit location. The user simply executes a standard chain flush and a small sample of ATPG test patterns to capture a resulting fail signature. Fail logs can then be imported into Broken Chain Analyzer, along with the test pattern for automated failure diagnosis.
Diagnosis is performed using our interactive GUI, or diagnose multiple sets of captured fail logs via an automated batch mode. Diagnosed chain bit fails can then be easily analyzed by Teseda’s Diagnostic Manager NetXY™ to identify the physical location of the individual net that is the likely causing the failure in the scan chain.
Teseda's Broken Chain Analyzer
- Automatically pinpoints defective flip-flop locations in broken scan chains
- Diagnoses scan chain flush and ATPG captured fail signatures
- Detects both hard (stuck-at) and soft (timing / voltage) faults in scan chains
- Compatible with Teseda Workbench™ (TWB) fail log files and STIL test patterns
- Results can be used with Teseda’s Diagnostic Manager NetXY™ to quickly identify physical cause of chain failure
Broken Chain Analyzer Features and Benefits
| Analyzes scan fail logs determine specific failing bit location within a defective scan chain | Cuts diagnosis of difficult to find scan chain issues by up to 80% |
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| Works with all EDA-generated patterns and captured scan fail logs | Finds faults in seconds — automated diagnosis based on captured test fail logs |
| Analyzes scan fail logs from any source | Works with any EDA-vendor generated scan test patterns Standalone diagnosis engine — run interactively or offline in batch mode |
| Identify the physical location of causes of scan chain faults | Combined with Teseda’s Diagnostic Manager NetXY, users can locate suspect failing nets in minutes, not hours or days |
Diagnose Scan Chain Issues Faster — Up to 80% Quicker to Root Cause
All SoC test strategies rely on fully operational scan chains within the design as the foundation of full testability - to set and sample internal logic values within the device. If any scan chains are blocked or marginally performing, design validation and failure analysis is severely limited and in many cases impossible until the chain issues are resolved.
Easily Identify Broken Scan Chains with the Chain Plot View
Teseda’s Broken Chain Analyzer addresses the fastest growing problem in the design of new semiconductor devices — failing or marginal scan chain operation. The Broken Chain Analyzer diagnoses common sources of scan chain issues, functional or timing/voltage related empowering you to resolve marginal performance issues such as improper shift operation, load / capture marginalities and scan enable issues. The diagnosis of blocked, broken or corrupted scan chains occurs in seconds, without requiring expensive and time-consuming probing techniques. Applying sophisticated captured-fail diagnosis techniques, the Broken Chain Analyzer can dramatically cut the time it takes to resolve scan chain functionality issues.