General Contacts:

E-Mail: info@teseda.com

Corporate Headquarters:
Teseda Corporation
6915 SW Macadam Ave.,
Suite 245
Portland, OR. 97219
USA

866 TESEDA1
866 837 3321
503 223 3315 (Tel)
503 223 3316 (Fax)
Teseda's silicon validation and analysis solutions exploit the full power of DFT, uniting Design, Test, Inspection, FA and Manufacturing to cut weeks from time-to-market and improve device yield and profitability. Visit this page frequently for updates and news regarding Teseda, including press releases and white papers. Also see our company background information.

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Teseda Introduces Three Advanced Failure Analysis Tools to Dramatically Reduce Root Cause Resolution and Improve RMA Cycle Time

PORTLAND, OR. — November 14, 2011 — Teseda Corporation, a leading provider of comprehensive diagnostic solutions for failure analysis and silicon debug, today announced three advanced failure analysis tools aimed at reducing root cause resolution, improving RMA cycle time and empowering failure analysis teams with new fault diagnosis methodologies. The Broken Chain Analyzer, Diagnostic Manager NetXY™ and DC Field Triage™ Package are fully compatible with Teseda’s V550™ and V520™ line of benchtop silicon debug and failure analysis test systems and the Teseda Workbench™ software silicon debug environment.

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Teradyne Signs Development Partnership with Teseda to Provide Next-Generation, Industry-Portable Scan Diagnosis Tools

NORTH READING, Mass. — Aug. 15, 2009 — Teradyne (NYSE: TER) announced the signing of an exclusive development agreement with Teseda Corporation to produce Scan Workbench™, a next-generation portable scan debug and yield enhancement tool. The tool will be based on industry-standard data protocols and the existing Teseda Workbench™(TWB) and Diagnostic Manager™(DM) products. Using Scan Workbench will allow Teradyne customers to better perform rapid silicon debug, design validation, failure analysis and yield monitoring resulting in decreased time-to-market and improved profitability. Scan Workbench provides a consistent debug and optimization environment on test platforms that support IEEE 1450.0-1999 Standard Test Interface Language (STIL) and the new STDF V4-2007 datalog standards. The software will initially be available on the Teradyne FLEX® and J750 platforms which will provide Scan Workbench with access to an installed base of over 5,000 testers. The new toolset will be shipping in Q2, 2010.

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TESEDA Corporation Signs Strategic Partnership Agreement with Q-Star Test nv

PORTLAND, OR. — April 30, 2009 — Teseda Corporation, a leading provider of comprehensive scan-based diagnostic and debug solutions for semiconductor debug, failure analysis and yield improvement announce a strategic partnership with Q-Star Test nv., of Brugge, Belgium. Teseda is now representing Q-Star Test and providing first line customer support for all of Q-Star’s products sold in North America.

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Teradyne and Teseda Providing Time-to-Market and Yield Enhancement Solutions for the UltraFLEX and J750 Test Platforms

NORTH READING, MA — October 28, 2008 — Teradyne (NYSE: TER) today announced their decision to collaborate with Teseda on an integration of the IG-XL™ programming environment with Teseda’s Diagnostic Manager Series toolset and WorkBench™ (TWB) software. As a result, customers will achieve an expanded capability to perform silicon debug, failure analysis and yield learning on Teradyne test platforms with a resulting decrease in time-to-market and improvement in profitability.

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Teseda and Mentor Graphics Partner to Speed Defect Diagnosis

PORTLAND, Oregon — October 24, 2008 — Teseda Corporation, a leading silicon validation and failure analysis diagnostic company, announced today that they have partnered with Mentor Graphics to link Mentor Graphic’s YieldAssist toolset with the Teseda Diagnostic Environment. This new capability will provide Teseda and Mentor customers with an integrated and truly layout-aware roundtrip flow that will accelerate their ability to rapidly diagnose scan failures down to the yield-limiting defects, and identify those defects in the physical layout. The portability and low cost of the Teseda platform will allow more users access to the new iterative diagnosis capability in YieldAssist. Coupled with the massive failure capture memory in the Teseda V-series systems, the YieldAssist tool will be able to iterate on even the most data-intensive defect candidates, such as defects in the scan logic.

The Teseda TWB Software will process test patterns from Mentor Graphics ATPG tools and run them directly on any Teseda TWB supported platforms, including the V520 and V550. The failure files are then passed to YieldAssist to analyze the test response and identify defect candidates. The resulting defect candidates can then be shown in the Teseda NetXY physical viewing environment. Optionally, the YieldAssist tool may be instructed to further isolate the candidates down to the most probable defect(s) by producing an iterative pattern set which can be immediately applied to the device-under-test though the Teseda Platform. This iterative process will yield the most probable defect candidate(s), which again may be highlighted in Teseda’s NetXY physical viewing environment.

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