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About Our Products
Teseda’s products are designed to be used by design, test and failure analysis engineers for use in silicon debug, failure analysis and yield improvement. Our products leverage the power of Design For Test (DFT) to enable faster, more productive, interactive diagnosis of scan-identified silicon defects.
- For first silicon debug, our products are used either on the bench or the production floor to quickly determine first-silicon functionality
- For failure analysis, our products dramatically reduce the turn-around time from fault to root-cause diagnosis
- For yield improvement, our products can accelerate the identification of scan-identified yield limiters by directly mapping observed scan failures to physical locations on the die
Diagnostic Manager NetXY™
NetXY is a powerful software tool that enables users to rapidly pinpoint the physical location of failing circuit elements in silicon by interpreting the Scan failures and leveraging the available DFT-based layout, ATPG and diagnosis data. NetXY interprets physical design information, diagnostic fault candidate reports and scan failure files, and highlights reported mismatches of failed test results of the capturing scan cell into a physical XY location on the die.
Diagnostic Manager NetXY
The Teseda V520™ and V550™ DFT-Enabled Engineering Test Systems
Teseda’s benchtop Engineering Test systems are commonly used in applications like first silicon debug at the die or packaged device level, IDDq testing, BIST testing, burn in, reliability testing and low volume production testing. Due to their ease of use, size, portability and low vibration our systems are widely used in advanced Failure Analysis applications such as dynamic laser stimulation (DLS), dynamic thermal imaging (XIVA/TIVA/LIVA or OBIRCH)
The Teseda V550 Engineering Test System
Our systems are designed to compatible with all common Failure Analysis diagnostic tools such as Hammamatsu™, SemiCAPs™, DCG™, or QFI™ emission microscopes. The systems also feature very low vibration, air cooling, 50 ohm triggering capabilities, deep capture memory up to 40 Mb per pin and built-in device pattern looping.
Our newest engineering test system, Teseda’s V550, offers 512 I/O pins, each with full per pin programmability, operating at speeds up to 100Mhz with a full 64Mb of per pin pattern memory in a small, portable, air-cooled desktop test system. Our smaller engineering test system, the V520, has 348 I/O pins operating at speeds up to 50Mhz, with a full 32Mb of per pin pattern memory also in a very small, air-cooled desktop test platform.
Teseda Workbench™
Teseda Workbench (TWB) provides the intuitive user interface to our hardware test systems. TWB imports STIL-based patterns typically generated by EDA tools such as Mentor Graphics FastScan™ or Synopsys TetraMax™, allows the user to assign pins, set levels and timing, run tests and then visualize and analyze the results in vector format or logic waveforms. TWB’s easy-to-use interface means the user can be up and running – seeing results in hours, not days.
The Teseda Workbench
The real power of Teseda Workbench (TWB) is in it's native ability to give the designer immediate visiibility into specifically where in the design failures are occuring, without tedious analysis of "seas of one's and zeros", counting offsets and bit locations, thus dramatically improving your
Scan Workbench™
Powerful Scan Fail Diagnostics Integrated into The Industries Most Popular ATE PlatformsScan Workbench integrates it's powerful, interactive scan fail debug environment available in TWB into Teradyne's™ IG-XL ATE programming environment. Scan Workbench brings DFT-aware capabilities into IG-XL - an interactive scan debug environment, full IEEE 1450-1999 (STIL) support and Teseda's powerful Chain Plot and Design View tools to the J750™, FLEX™ and UltraFLEX™ families of production testers.
Scan Workbench for IG-XL
Improve your teams debug efficiency - greatly improve the scan fail debug capabilities on the ATE systems you are already using. By adding Scan Workbench to your existing IG-XL environment, you can dramatically shorten your silicon debug time, turning days of debug into hours.
DC Field Triage™ Package
Teseda’s DC Field Triage Package provides the user with easy to use, automated screening tools for DC related device failures. Designed for use by field personnel, the DC Field Triage Package puts device failure triage into the design and field support centers, enabling fast, timely and detailed responses to your customer’s quality concerns. Since first-level field screening is done in the field, factory failure analysis tasks are offloaded by as much as 40%.
Device Curve Traces Taken with the DC Field Triage Package
Broken Chain Analyzer
Teseda’s Broken Chain Analyzer focuses on accelerating the diagnosis of defective scan chains, a growing issue in failure analysis of newer SoC designs that rely on larger numbers of lengthier scan chains for full testability and fault coverage. At line widths of 65nm and below, scan chain related issues amount to greater than 30% of overall scan failures. Broken Chain Analyzer fully exploits the power of your existing DFT-based tests to automatically analyze captured tester fail logs and detect all common causes of scan chain failures - both hard (stuck-at fails) and soft (timing or voltage-related fails) down to the failing bit location.
Teseda's Broken Chain Analyzer
Defect Diagnosis Service
Contract with Teseda’s FA experts using Teseda world-class FA tools to localize, isolate and confirm the location of failures on your design. You engage at the level you need to add capabilities to your FA processes. Teseda FA Service will provide you with a fast cost effective method to improve your FA results.
Defect Localization |
Defect Isolation |
Defect Confirmation |
