Silicon Validation; Failure
Analysis; Yield Improvement; Yield Assurance:
Teseda Products help you address your greatest
time to market or time to money needs.
Reduce time to production, accelerate yield
learning, maximize profits. These goals have prompted IC companies to adopt Design-for-Test (DFT)
methodologies. But traditional DFT tools offer only a limited connection
between your design, wafer inspection, test, failure analysis and manufacturing
environments, resulting in longer times for new silicon debug in engineering
and debug of problems on the test floor. Teseda's validation and analysis
solutions exploit the full power of DFT, uniting design, test, inspection,
FA and manufacturing to cut weeks from time-to-money and improve device
yield and profitability.
It's all about Time, Yield and Profit. Teseda's silicon
validation and analysis solutions increase your return-on-investment
by integrating your current investments in design, DFT and test software,
engineering and test hardware platforms and manufacturing process
flows. By leveraging DFT throughout the product cycle to speed silicon
debug, manufacturing ramp, failure analysis and yield learning, Teseda's
solutions speed yield enhancement and improve profits for semiconductor
companies.
Validated Solutions and key Partnerships for Maximum Quality.
Teseda silicon validation and analysis solutions support all of the
major Electronic Design Automation (EDA) vendors, including Cadence
Design Systems, LogicVision, Magma Design Automation, Mentor Graphics
and Synopsys. Teseda can also work with Automated Test Equipment (ATE)
vendors to provide support on today's leading test hardware platforms.
With Teseda's solutions, you will:
- Cut Weeks from Silicon Debug. Teseda productivity tools feature
DFT-Intelligent™ views of test results, showing both the DFT and design-hierarchy
views of information, together with the traditional test vector view,
to speed test debug and get new silicon up and running faster, cutting
weeks off time-to-money.
- Resolve Problems on the Test Floor. The Teseda
WorkBench™ works with your ATE or the Teseda V-series hardware platforms
to facilitate design and test collaboration, leveraging
design and test views of test results to rapidly determine whether
the problem lies in the DFT or the test program. Resolving test floor
problems more quickly gets you to revenue faster.
- Cut Weeks from Failure Analysis. Teseda's DFT-Intelligent software
allows the failure analysis engineer to log test errors in the right
format for DFT tools to automatically isolate the location of a device
defect. This automation cuts weeks from failure analysis, so both
design and manufacturing problems causing low yields can be more quickly
understood and addressed, increasing profits.
Enable rapid Yield Learning. By automating error logging and
diagnosis, and closing the loop with inspection tools, semiconductor
vendors can statistically analyze much larger samples of defect types
and defective devices than is practical in the traditional failure analysis
flow. Teseda tools mine more defect data to detect yield issues faster,
and Teseda continues to work with the leading semiconductor companies
and equipment vendors to improve the automation and effectiveness of
data mining for yield analysis and improvement. |
