Scan Workbench integrates Teseda’s award-winning DFT-aware, interactive scan fail debug environment into the IG-XL environment. Scan Workbench fully exploits the power of your DFT investment, enabling design, test, manufacturing and FA teams to work together to reduce time to production, accelerate yield learning, and maximize profits.
Scan Workbench for IG-XL
Scan Workbench leverages the power of utilizing existing DFT structures designed into your silicon. Since the Scan Workbench toolset automatically comprehends the device’s DFT-embedded design heirarchy, scan-detected failures can be mapped to specific scan chains, scan cells and design blocks without the the need for tedious decipherering of pin and cycle failure information. Scan Workbench’s DFT-aware environment adds efficient debugging of common Scan-detected device failures, such as broken scan chains and scan-related timing violations, to IG-XL. Failures captured can be exported to be analyzed by scan fault diagosis and analysis tools such as Mentor Graphics YieldAssist™, Synopsys TetraMAX™ and Teseda’s Diagnostic Manager NetXY™.
Scan Workbench is available for Teradyne’s J750™, FLEX™ and UltraFLEX™ families of testers. Improve your teams debug efficiency on the systems you are already using with minimal training. By adding Scan Workbench to your existing IG-XL environment, you can dramatically shorten your silicon debug time, turning days of debug into hours.