 |
 |
 |
 |
 |
 |
 |
Scan Validation, Silicon Debug and Failure Analysis in Days — Not Weeks
Teseda Workbench (TWB) operates interactively on the V520 and V550 engineering test systems to provide failure information in terms of the design features where the failure occurred. TWB provides a comprehensive, designer-friendly set of tools for functional and scan-based debug and characterization. With its intuitive interface and native support for embedded DFT structures, you can turn days of debug time into hours.
The Teseda Workbench Chain Plot Tool
- Comprehensive interactive device debug and failure analysis software toolset
- Created for designers and failure analysis engineers – fast, intuitive interface
- Uses STIL files generated by ATPG tools without translation
- Create a new device test in minutes
- Interactively change timing, voltages, edit patterns and view vector errors
- Automatically maps scan fails to specific design locations - scan chain, scab cell, design block and scan cell instance name
- Outputs scan fail logs that can be further analyzed by EDA diagnosis tools or Diagnostic Manager NetXY™ to isolate defects to the physical location
The Teseda Workbench Logic Waveform Display Tool
Teseda WorkBench comes with a full suite of interactive debug tools such as a the Chain Plot, the Design / Scan View tool, Shmoo tool and, Pattern Display with logic waveform viewing. TWB allows the user to easily change device settings such as timing, levels and logic states, run tests and see results. TWB leverages the built-in DFT-structures to identify the specific scan cells that captured the failure and then report the failure in terms of the design hierarchy.
The Teseda Workbench Vector Display
Benefits of Teseda Workbench:
- Faster, more accurate silicon debug in your lab, not on the production floor
- Leverages your DFT investment to accelerate real-time, interactive silicon validation, debug and failure analysis
- Intuitive graphical user interface and design-aware failure results means you debug faster and with a common language (test names, pin names, block and design hierarchy)
- Reduce failure analysis fault diagnosis time by up to 80%