Diagnostic Manager NetXY quickly maps scan test failures to the physical location on the die, reducing the time to fault resolution by up to 90%. The newest release of Diagnostic Manager NetXY now includes logic cone and physical scan chain tracing - powerful new diagnosis features to address EDA-vendor independent failure diagnosis.
This powerful scan fail diagnostic tool combines with our Teseda Workbench environment and V520 or V550 engineering test systems, enabling the user to very quickly identify the location of faults such as opens and bridges.
See more about NetXY on our Products page.
Teseda provides hardware and software solutions used for silicon debug, failure analysis and yield enhancement. Teseda's products help your engineers debug first silicon quickly, reducing time-to-market and achieving rapid high-yield ramp of new designs. Our typical users are involved in design, product engineering and failure analysis of complex new SoC designs. Teseda's customers include most of the leading semiconductor companies around the world.
The Teseda V520 DFT-Enabled Engineering Test System
With the widespread adoption of Design-for-Test (DFT) in the industry, design teams are leveraging the power of EDA to increase design productivity, shorten test generation and improve fault coverage. But existing DFT tools only offer limited communication between your design, debug, manufacturing and failure analysis environments, resulting in longer times for new silicon debug in engineering and debug of problems on the test floor. Teseda's silicon debug, failure analysis and yield solutions fully exploit the power of DFT, uniting design, test, inspection, FA and manufacturing to cut weeks from successful silicon ramp up, dramatically improving time-to-market for your newest products.
"Providing innovative solutions for silicon debug, failure analysis and yield improvement, dramatically improving our customer's ability to ship new designs on-time and with high yield."